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cy2305/cy2309 low cost 3.3 v zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07140 rev. *s revised march 13, 2014 low cost 3.3 v zero delay buffer features 10 mhz to 100/133 mhz operating range, compatible with cpu and pci bus frequencies zero input-output propagation delay 60-ps typical cycle-to-cyc le jitter (high drive) multiple low skew outputs ? 85 ps typical output-to-output skew ? one input drives five outputs (cy2305) ? one input drives nine outputs, grouped as 4 + 4 + 1 (cy2309) compatible with pentium-based systems test mode to bypass phase-locked loop (pll) (cy2309) packages: ? 8-pin, 150-mil soic package (cy2305) ? 16-pin 150-mil soic or 4.4-mm tssop (cy2309) 3.3 v operation commercial and industrial temperature ranges functional description the cy2309 is a low-cost 3.3 v zero delay buffer designed to distribute high speed clocks and is available in a 16-pin soic or tssop package. the cy2305 is an 8-pin version of the cy2309. it accepts one reference input, and drives out five low skew clocks. the -1h versions of each device operate at up to 100-/133 mhz frequencies, and have higher drive than the -1 devices. all parts have on-chip plls which lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. the cy2309 has two banks of four outputs each, which can be controlled by the select inputs as shown in ?select input decoding for cy2309? on page 4. if all output clocks are not required, bankb can be three-stated. the select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. the cy2305 and cy2309 plls enter a power-down mode when there are no rising edges on the ref input. in this state, the outputs are three-stated and the pll is turned off, resulting in less than 25.0 ? a current draw for these parts. the cy2309 pll shuts down in one additional case as shown in ?select input decoding for cy2309? on page 4. multiple cy2305 and cy2309 devices can accept the same input clock and distribute it. in this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. the cy2305/cy2309 is available in two or three different configurations, as shown in ?ordering information for cy2305? on page 13. the cy2305-1/cy2309-1 is the base part. the cy2305-1h/ cy2309-1h is the high-drive version of the -1, and its rise and fall times are much faster than the -1. pll mux select input ref s2 s1 clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 decoding clkout logic block diagram
cy2305/cy2309 document number: 38-07140 rev. *s page 2 of 22 contents pinouts .............................................................................. 3 select input decoding for cy2309 .................................. 4 zero delay and skew control .......................................... 4 absolute maximum conditions ....................................... 5 operating conditions for cy2305sc-xx and cy2309sc-xx commercial temperature devices ......... 5 electrical characteristi cs for cy2305sc-xx and cy2309sc-xx commercial temperature devices ......... 5 switching characteristi cs for cy2305sc-1 and cy2309sc-1 commercial temperature devices ........... 5 switching characteristics for cy2305sc-1h and cy2309sc-1h commercial temperature devices ......... 6 operating conditions for cy2305si-xx and cy2309si-xx industrial temperature devices ............... 6 electrical characteristi cs for cy2305si-xx and cy2309si-xx industrial temperature devices ............... 7 switching characteristics for cy2305si-1 and cy2309si-1 industrial temper ature devices ........... ...... 7 switching characteristics for cy2305si-1h and cy2309si-1h industrial temper ature devices ............... 8 switching waveforms ...................................................... 8 typical duty cycle [ 17 ] and i dd trends [ 18 ] for cy2305-1 and cy2309-1 ........................................... 10 typical duty cycle [ 19 ] and idd trends [ 20 ] for cy2305-1h and cy2309-1h ...................................... 11 test circuits .................................................................... 12 ordering information for cy2305 ............ .............. ........ 13 ordering information for cy2309 ............ .............. ........ 13 ordering code definitions ..... .................................... 14 package drawing and dimensions ............................... 15 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 errata ............................................................................... 18 part numbers affected .............................................. 18 cy2305/cy2309 errata summar y .............. .............. 19 cy2305/cy2309 qualification st atus ......... .............. 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 22 worldwide sales and design s upport ......... .............. 22 products .................................................................... 22 psoc? solutions ...................................................... 22 cypress developer community ................................. 22 technical support ................. .................................... 22
cy2305/cy2309 document number: 38-07140 rev. *s page 3 of 22 pinouts figure 1. pin diagram - cy2305 figure 2. pin diagram - cy2309 table 1. pin description for cy2305 pin signal description 1 ref [1] input reference frequency, 5-v tolerant input 2 clk2 [2] buffered clock output 3 clk1 [2] buffered clock output 4 gnd ground 5 clk3 [2] buffered clock output 6v dd 3.3-v supply 7 clk4 [2] buffered clock output 8 clkout [2] buffered clock output, internal feedback on this pin table 2. pin description for cy2309 pin signal description 1 ref [1] input reference frequency, 5-v tolerant input 2 clka1 [2] buffered clock output, bank a 3 clka2 [2] buffered clock output, bank a 4v dd 3.3-v supply 5 gnd ground 6 clkb1 [2] buffered clock output, bank b 7 clkb2 [2] buffered clock output, bank b 8 s2 [3] select input, bit 2 9 s1 [3] select input, bit 1 10 clkb3 [2] buffered clock output, bank b 11 clkb4 [2] buffered clock output, bank b 12 gnd ground 1 2 3 4 5 8 7 6 ref clk2 clk1 gnd v dd clkout clk4 clk3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 clkout clka4 clka3 v dd gnd clkb4 clkb3 s1 notes 1. weak pull down. 2. weak pull down on all outputs. 3. weak pull ups on these inputs.
cy2305/cy2309 document number: 38-07140 rev. *s page 4 of 22 figure 3. ref. input to clka/clkb delay vs. loading difference between clkout and clka/clkb pins zero delay and skew control all outputs must be uniformly loaded to achieve zero delay bet ween the input and output. because the clkout pin is the internal feedback to the pll, its relative loading can adjust the input-output delay. this is shown in the above graph. for applications requiring zero input-output delay, all outputs, including clkout, must be equally loaded. even if clkout is no t used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. if input to output delay adjustments are required, use figure 3 to calculate loading differences betw een the clkout pin and other outputs. for zero output-output skew, be sure to load all outputs equally. for further information, refer to the application note titled ? cy2305 and cy2309 as pci and sdram buffers .? 13 v dd 3.3-v supply 14 clka3 [4] buffered clock output, bank a 15 clka4 [4] buffered clock output, bank a 16 clkout [4] buffered output, internal feedback on this pin select input decoding for cy2309 s2 s1 clock a1?a4 clock b1?b4 clkout [5] output source pll shutdown 0 0 three-state three-state driven pll n 0 1 driven three-state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n table 2. pin description for cy2309 pin signal description notes 4. weak pull down on all outputs 5. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew be tween the reference and output.
cy2305/cy2309 document number: 38-07140 rev. *s page 5 of 22 absolute maximum conditions supply voltage to ground potenti al ...............?0.5 v to +7.0 v dc input voltage (except ref) .......... ?0.5 v to v dd + 0.5 v dc input voltage ref .................. ............ ..........?0.5 v to 7 v storage temperature .. ............... .............. ... ?65c to +150c junction temperature.................................................. 150c static discharge voltage (per mil-std-883, method 3015) .. ............. ........... > 2,000 v operating conditions for cy2305sc-xx and cy 2309sc-xx commercial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) 0 70 c c l load capacitance, below 100 mhz ? 30 pf c l load capacitance, from 100 mhz to 133 mhz ? 10 pf c in input capacitance ? 7 pf t pu power-up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics fo r cy2305sc-xx and cy2309sc- xx commercial temperature devices parameter description test conditions min max unit v il input low voltage [6] ?0.8v v ih input high voltage [6] 2.0 ? v i il input low current v in = 0 v ? 50.0 ? a i ih input high current v in = v dd ? 100.0 ? a v ol output low voltage [7] i ol = 8 ma (?1) i oh = 12 ma (?1h) ?0.4v v oh output high voltage [7] i oh = ?8 ma (?1) i ol = ?12 ma (?1h) 2.4 ? v i dd (pd mode) power-down supply current ref = 0 mhz ? 12.0 ? a i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v ss ?32.0ma switching characteristics for cy2305sc-1 and cy2309sc-1 commercial temperature devices parameter [10] name test conditions min typ. max unit t1 output frequency 30-pf load 10-pf load 10 10 ?100 133.33 mhz mhz t dc duty cycle [7] = t 2 ? t 1 measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % t3 rise time [7] measured between 0.8 v and 2.0 v ? ? 2.50 ns t 4 fall time [7] measured between 0.8 v and 2.0 v ? ? 2.50 ns t 5 output-to-output skew [7] all outputs equally loaded ? 85 250 ps t 6a delay, ref rising edge to clkout rising edge [7] measured at v dd /2 ? 0 350 ps notes 6. ref input has a threshold voltage of v dd /2. 7. parameter is guaranteed by design and charac terization. not 100% tested in production.
cy2305/cy2309 document number: 38-07140 rev. *s page 6 of 22 t 6b delay, ref rising edge to clkout rising edge [8] measured at v dd /2. measured in pll bypass mode, cy2309 device only. 158.7 ns t 7 device-to-device skew [8] measured at v dd /2 on the clkout pins of devices ??700 ps t j cycle-to-cycle jitter [8] measured at 66.67 mhz, loaded outputs ?70200 ps t lock pll lock time [8,9, 10] stable power supply, valid clock presented on ref pin ??1.0 ms switching characteristics for cy2305sc-1h and cy2309sc-1h commercial temperature devices parameter [10] name description min typ. max unit t 1 output frequency 30 pf load 10 pf load 10 10 ?100 133.33 mhz mhz t dc duty cycle [8] = t 2 ? t 1 measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % t dc duty cycle [8] = t 2 ? t 1 measured at 1.4 v, f out < 50 mhz 45.0 50.0 55.0 % t 3 rise time [8] measured between 0.8 v and 2.0 v ? ? 1.50 ns t 4 fall time [8] measured between 0.8 v and 2.0 v ? ? 1.50 ns t 5 output-to-output skew [8] all outputs equally loaded ? 85 250 ps t 6a delay, ref rising edge to clkout rising edge [8] measured at v dd /2 ? ? 350 ps t 6b delay, ref rising edge to clkout rising edge [8] measured at v dd /2. measured in pll bypass mode, cy2309 device only. 158.7 ns t 7 device-to-device skew [8] measured at v dd /2 on the clkout pins of devices ??700ps t 8 output slew rate [8] measured between 0.8 v and 2.0 v using test circuit #2 1? v/ns t j cycle-to-cycle jitter [8] measured at 66.67 mhz, loaded outputs ?60200 ps t lock pll lock time [8,9, 10] stable power supply, valid clock presented on ref pin ??1.0ms operating conditions for cy 2305si-xx and cy2309si-xx indus trial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (amb ient temperature) ?40 85 c c l load capacitance, below 100 mhz ? 30 pf c l load capacitance, from 100 mhz to 133 mhz ? 10 pf c in input capacitance ? 7 pf switching characteristics for cy2305sc-1 and cy2309sc-1 commercial temperature devices parameter [10] name test conditions min typ. max unit notes 8. parameter is guaranteed by design and charac terization. not 100% tested in production. 9. the clock outputs are undefined until pll is locked. 10. for on the fly change in reference input frequency, pll lock ti me is only guaranteed when stop time between change in input reference frequency is > 10 s, figure 9 . 11. all parameters specified with loaded outputs.
cy2305/cy2309 document number: 38-07140 rev. *s page 7 of 22 electrical characteristics for cy2305si-xx a nd cy2309si-xx industrial temperature devices parameter description test conditions min max unit v il input low voltage [12] ?0.8v v ih input high voltage [12] 2.0 ? v i il input low current v in = 0 v ? 50.0 ? a i ih input high current v in = v dd ? 100.0 ? a v ol output low voltage [13] i ol = 8 ma (?1) i oh =12 ma (?1h) ?0.4v v oh output high voltage [13] i oh = ?8 ma (?1) i ol = ?12 ma (?1h) 2.4 ? v i dd (pd mode) power-down supply current ref = 0 mhz ? 25.0 ? a i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v ss ?35.0ma switching characteristics fo r cy2305si-1 and cy2309si-1 indu strial temperature devices parameter [13] name test conditions min typ max unit t1 output frequency 30 pf load 10 pf load 10 10 ?100 133.33 mhz mhz t dc duty cycle [13] = t 2 ? t 1 measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % t3 rise time [13] measured between 0.8 v and 2.0 v ? ? 2.50 ns t 4 fall time [13] measured between 0.8 v and 2.0 v ? ? 2.50 ns t 5 output-to-output skew [13] all outputs equally loaded ? 85 250 ps t 6a delay, ref rising edge to clkout rising edge [13] measured at v dd /2 ? ? 350 ps t 6b delay, ref rising edge to clkout rising edge [13] measured at v dd /2. measured in pll bypass mode, cy2309 device only. 158.7ns t 7 device-to-device skew [13] measured at v dd /2 on the clkout pins of devices ? ? 700 ps t j cycle-to-cycle jitter [13] measured at 66.67 mhz, loaded outputs ? 70 200 ps t lock pll lock time [9, 10, 13] stable power supply, valid clock presented on ref pin ??1.0ms notes 12. ref input has a threshold voltage of v dd /2. 13. parameter is guaranteed by design and characterization. not 100% tested in production. 14. all parameters specified with loaded outputs
cy2305/cy2309 document number: 38-07140 rev. *s page 8 of 22 switching characteristics for cy2305si-1h and cy2309si-1h i ndustrial temperature devices parameter [14] name description min typ max unit t 1 output frequency 30 pf load 10 pf load 10 10 ?100 133.33 mhz mhz t dc duty cycle [16] = t 2 ? t 1 measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % t dc duty cycle [16] = t 2 ? t 1 measured at 1.4 v, f out < 50 mhz 45.0 50.0 55.0 % t 3 rise time [16] measured between 0.8 v and 2.0 v ? ? 1.50 ns t 4 fall time [16] measured between 0.8 v and 2.0 v ? ? 1.50 ns t 5 output-to output skew [16] all outputs equally loaded ? 85 250 ps t 6a delay, ref rising edge to clkout rising edge [16] measured at v dd /2 ? ? 350 ps t 6b delay, ref rising edge to clkout rising edge [16] measured at v dd /2. measured in pll bypass mode, cy2309 device only. 158.7ns t 7 device-to-device skew [16] measured at v dd /2 on the clkout pins of devices ? ? 700 ps t 8 output slew rate [16] measured between 0.8 v and 2.0 v using test circuit #2 1??v/ns t j cycle-to-cycle jitter [16] measured at 66.67 mhz, loaded outputs ? 60 200 ps t lock pll lock time [9,10,16] stable power supply, valid clock presented on ref pin ??1.0ms switching waveforms notes 15. all parameters specified with loaded outputs. 16. parameter is guaranteed by design and c haracterization. not 100% tested in production. t 1 t 2 1.4 v 1.4 v 1.4 v figure 4. duty cycle timing output t 3 3.3 v 0 v 0.8 v 2.0 v 2.0 v 0.8 v t 4 figure 5. all outputs rise/fall time 1.4 v 1.4 v t 5 output output figure 6. output-output skew
cy2305/cy2309 document number: 38-07140 rev. *s page 9 of 22 switching waveforms v dd /2 t 6 input output v dd /2 figure 7. input-output propagation delay v dd /2 v dd /2 t 7 clkout, device 1 clkout, device 2 figure 8. device-device skew figure 9. stop time between change in input reference frequency stop time
cy2305/cy2309 document number: 38-07140 rev. *s page 10 of 22 typical duty cycle [17] and i dd trends [18] for cy2305-1 and cy2309-1 duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (% ) 33 mhz 66 mhz 100 mhz duty cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (for 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 0123456789 # of loaded outputs idd (ma) 33 mhz 66 mhz 100 mhz idd vs number of loaded outputs (for 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 0123456789 # of loaded outputs idd (ma) 33 mhz 66 mhz 100 mhz notes 17. duty cycle is taken from typical chip measured at 1.4 v. 18. i dd data is calculated from i dd = i core + ncvf, where i core is the unloaded current. (n = # of outputs; c = capacitance load per output (f); v = supply voltage (v); f = frequency (hz)).
cy2305/cy2309 document number: 38-07140 rev. *s page 11 of 22 typical duty cycle [19] and idd trends [20] for cy2305-1h and cy2309-1h notes 19. duty cycle is taken from typical chip measured at 1.4 v. 20. i dd data is calculated from i dd = i core + ncvf, where i core is the unloaded current. (n = # of outputs; c = capacitance load per output (f); v = supply voltage (v); f = frequency (hz)). duty cycle vs vdd (for 30 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz dut y cycle vs vdd (for 15 pf loads over frequency - 3.3v, 25c) 40 42 44 46 48 50 52 54 56 58 60 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) duty cycle (%) 33 mhz 66 mhz 100 mhz 133 mhz duty cycle vs frequency (for 30 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c duty cycle vs frequency (for 15 pf loads over temperature - 3.3v) 40 42 44 46 48 50 52 54 56 58 60 20 40 60 80 100 120 140 frequency (mhz) duty cycle (%) -40c 0c 25c 70c 85c idd vs number of loaded outputs (for 30 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 160 0123456789 # of loaded outputs idd (ma) 33 mhz 66 mhz 100 mhz idd vs number of loaded outputs (for 15 pf loads over frequency - 3.3v, 25c) 0 20 40 60 80 100 120 140 160 0123456789 # of loaded outputs idd (ma) 33 mhz 66 mhz 100 mhz
cy2305/cy2309 document number: 38-07140 rev. *s page 12 of 22 test circuits 0.1 ? f v dd 0.1 ? f v dd clk out c load outputs gnd gnd 0.1 ? f v dd 0.1 ? f v dd 10 pf outputs gnd gnd 1 k ? 1 k ? test circuit # 1 test circuit # 2 for parameter t 8 (output slew rate) on -1h devices
cy2305/cy2309 document number: 38-07140 rev. *s page 13 of 22 ordering information for cy2305 ordering code package type operating range cy2305sc-1 8-pin 150-mil soic commercial cy2305sc-1t 8-pin 150-mil soic ? tape and reel commercial cy2305si-1h 8-pin 150-mil soic industrial cy2305si-1ht 8-pin 150-mil soic ? tape and reel industrial pb-free cy2305sxc-1 8-pin 150-mil soic commercial CY2305SXC-1T 8-pin 150-mil soic ? tape and reel commercial cy2305sxi-1 8-pin 150-mil soic industrial cy2305sxi-1t 8-pin 150-mil soic ? tape and reel industrial cy2305sxc-1h 8-pin 150-mil soic commercial cy2305sxc-1ht 8-pin 150-mil soic ? tape and reel commercial cy2305sxi-1h 8-pin 150-mil soic industrial cy2305sxi-1ht 8-pin 150-mil soic ? tape and reel industrial ordering information for cy2309 ordering code package type operating range cy2309sc-1h 16-pin 150-mil soic commercial cy2309sc-1ht 16-pin 150-mil soic ? tape and reel commercial cy2309zc-1h 16-pin 4.4-mm tssop commercial cy2309zc-1ht 16-pin 4.4-mm tssop ? tape and reel commercial pb-free cy2309sxc-1 16-pin 150-mil soic commercial cy2309sxc-1t 16-pin 150-mil soic ? tape and reel commercial cy2309sxi-1 16-pin 150-mil soic industrial cy2309sxi-1t 16-pin 150-mil soic ? tape and reel industrial cy2309sxc-1h 16-pin 150-mil soic commercial cy2309sxc-1ht 16-pin 150-mil soic ? tape and reel commercial cy2309sxi-1h 16-pin 150-mil soic industrial cy2309sxi-1ht 16-pin 150-mil soic ? tape and reel industrial cy2309zxc-1h 16-pin 4.4-mm tssop commercial cy2309zxc-1ht 16-pin 4.4-mm tssop ? tape and reel commercial cy2309zxi-1h 16-pin 4.4-mm tssop industrial cy2309zxi-1ht 16-pin 4.4-mm tssop ? tape and reel industrial
cy2305/cy2309 document number: 38-07140 rev. *s page 14 of 22 ordering code definitions cy 2305 s (x) c ? 1 (h) (t) tape and reel output drive: 1 = standard drive 1h = high drive temperature range: c = commercial i = industrial package: s = soic, leaded z = tssop, leaded sx = soic, pb-free zx = tssop, pb-free base device part number 2305 = 5-output zero delay buffer 2309 = 9-output zero delay buffer company id: cy = cypress
cy2305/cy2309 document number: 38-07140 rev. *s page 15 of 22 package drawing and dimensions figure 10. 8-pin (150-mil) soic s8 51-85066 *f
cy2305/cy2309 document number: 38-07140 rev. *s page 16 of 22 figure 11. 16-pin (150-mil) soic s16 figure 12. 16-pin tssop 4.40 mm body z16.173 51-85068 *e 51-85091 *d
cy2305/cy2309 document number: 38-07140 rev. *s page 17 of 22 acronyms document conventions units of measure acronym description pci personal computer interconnect pll phase locked loop sdram synchronous dynamic random access memory soic small outline integrated circuit tssop thin small outline package zdb zero delay buffer symbol unit of measure ? c degree celsius a microampere ma milliampere ms millisecond mhz megahertz ns nanosecond pf picofarad ps picosecond vvolt
cy2305/cy2309 document number: 38-07140 rev. *s page 18 of 22 errata this section describes the errata for cypress zero delay clock bu ffers of the family cy2305/cy23 09. details include errata trig ger conditions, scope of impact, available work around, and silicon revision applicability. contact your local cypress sales re presentative if you have questions. part numbers affected part number device characteristics cy2305sc-1 all variants cy2305sc-1t all variants cy2305sc-1h all variants cy2305sc-1ht all variants cy2305si-1h all variants cy2305si-1ht all variants cy2305sxc-1 all variants CY2305SXC-1T all variants cy2305sxi-1 all variants cy2305sxi-1h all variants cy2305sxc-1ht all variants cy2305sxi-1h all variants cy2305sxi-1ht all variants cy2309nzsxc-1h all variants cy2309nzsxc-1ht all variants cy2309nzsxi-1h all variants cy2309nzsxi-1ht all variants cy2309sc-1ht all variants cy2309sxc-1h all variants cy2309sxc-1ht all variants cy2309sxi-1h all variants cy2309sxi-1ht all variants cy2309zc-1h all variants cy2309zc-1ht all variants cy2309zxc-1h all variants cy2309zxc-1ht all variants cy2309zxi-1h all variants cy2309zxi-1ht all variants cy2309sxc-1 all variants cy2309sxc-1t all variants cy2309sxi-1 all variants cy2309sxi-1t all variants cy2309sc-1 all variants cy2309sc-1t all variants cy2309sxc-1 all variants cy2309sxc-1t all variants cy2309sxi-1 all variants cy2309sxi-1t all variants
cy2305/cy2309 document number: 38-07140 rev. *s page 19 of 22 cy2305/cy2309 errata summary cy2305/cy2309 qualification status product status: in production qualification report la st updated on 11/27/2012 ( http://www.cypress.com/?rid=72595 ) 1. start up lock time issue problem definition output of cy2305/cy2309 fails to locks wi thin 1 ms (as per data sheet spec) parameters affected pll lock time trigger condition(s) start up scope of impact it can impact the performance of system and its throughput workaround apply reference input (refclk) before power up (vdd) input noise propagates to output due to absence of reference input signal during power up. if reference input is present during power up , the noise will not propagate to output and device will start no rmally without problems. fix status this issue is due to design marginality. two minor design modifications have been made to address this problem. ? addition of vco bias detector block as shown in the following fi gure which keeps comparator powe r down till vco bias is present and thereby eliminating the prop agation of noise to feedback. ? bias generator enhancement for successful initialization. items part number silicon revision fix status start up lock time issue [cy2305] all b silicon fixed. new silicon available from ww 25 of 2011 start up lock time issue [cy2309] all b silicon fixed. new silicon available from ww 10 of 2013
cy2305/cy2309 document number: 38-07140 rev. *s page 20 of 22 document history page document title: cy2305/cy2309, low cost 3.3 v zero delay buffer document number: 38-07140 revision ecn orig. of change submission date description of change ** 110249 szv 10/19/01 change from spec number: 38-00530 to 38-07140 *a 111117 ckn 03/01/02 added t6b row to the switching characteristics table; also added the letter ?a? to the t6a row corrected the table title from cy2305sc-ih and cy2309sc-ih to cy2305si-ih and cy2309si-ih *b 117625 hwt 10/21/02 added eight-pin tssop packages (cy2305zc-1 and cy2305zc-1t) to the ordering information table. added the tape and reel option to all the existing packages: cy2305sc-1t, cy2305si-1t, cy2305sc-1ht, cy2305si-1ht, cy2305zc-1t, cy2309sc-1t, cy2309si-1t, cy2309sc-1ht, cy2309si-1ht, cy2309zc-1ht, cy2309zi-1ht *c 121828 rbi 12/14/02 power up requirements added to operating conditions information *d 131503 rgl 12/12/03 added lead-free for all the devices in the ordering information table *e 214083 rgl see ecn added a lead-free with the new coding for all soic devices in the ordering information table *f 291099 rgl see ecn added tssop lead-free devices *g 390582 rgl see ecn added typical values for jitter *h 2542461 aesa 07/23/08 updated template. added note ?not recommended for new designs.? added part number cy2305esxc-1, cy2305esxc-1t, cy2305esxi-1, cy2305esxi-1t, cy2305esxc-1h, cy2305esxc-1ht, cy2305esxi-1h, cy2305esxi-1ht, cy2309esxc-1, cy2309esxc-1t, cy2309esxi-1, cy2309esxi-1t, cy2309esxc-1h, cy2309esxc-1ht, cy2309esxi-1h, cy2309esxi-1ht, cy2309ezxc-1h, cy2309ezxc-1ht, cy2309ezxi-1h, and cy2309ezxi-1ht in ordering information table. removed part number cy2305szc-1, cy2305szc-1t, cy2305szi-1, cy2305szi-1t, cy2305szc-1h, cy2305szc-1ht, cy2305szi-1h, cy2305szi-1ht, cy2309szc-1, cy2309szc-1t, cy2309szi-1, cy2309szi-1t, cy2309szc-1h, cy2309szc-1ht, cy2309szi-1h, cy2309szi-1ht, cy2309zzc-1h, cy2309zzc-1ht, cy2309zi-1h, cy2309zi-1ht, cy2309zzi-1h, and cy2309zzi-1ht in ordering information table. changed lead-free to pb-free. *i 2565153 aesa 09/18/08 removed part number cy2305esxc-1, cy2305esxc-1t, cy2305esxi-1, cy2305esxi-1t, cy2305esxc-1h, cy2305esxc-1ht, cy2305esxi-1h, cy2305esxi-1ht, cy2309esxc-1, cy2309esxc-1t, cy2309esxi-1, cy2309esxi-1t, cy2309esxc-1h, cy2309esxc-1ht, cy2309esxi-1h, cy2309esxi-1ht, cy2309ezxc-1h, cy2309ezxc-1ht, cy2309ezxi-1h, and cy2309ezxi-1ht in ordering information table. removed note references to note 10 in pb-free sections of ordering infor- mation table. changed idd (pd mode) from 12.0 to 25.0 ? a for commercial temperature devices deleted duty cycle parameters for f out < ? 50 mhz commercial and industrial devices. *j 2673353 kvm / pyrs 03/13/09 reverted idd (pd mode) and duty cycle parameters back to the values in revision *h: changed idd (pd mode) from 25 to 12 ? a for commercial devices. added duty cycle parameters for f out < ? 50 mhz for commercial and industrial devices.
cy2305/cy2309 document number: 38-07140 rev. *s page 21 of 22 *k 2904641 kvm 04/05/10 removed parts cy2305si-1, cy2305si-1t, cy2309si-1, cy2309si-1h, cy2309si-1ht, cy2309si-1t from ordering information. updated package diagram *l 3047136 kvm 10/04/2010 added table of contents, ordering code definition, acronyms and units tables. updated 16-pin tssop package diagram. *m 3146330 cxq 01/18/2011 added ?not recommended for new designs? statement to features on page 1. added ?not recommended for new designs? footnote to all parts in the ordering information table. *n 3241160 bash 05/09/2011 added footnote 9 on page 6 (cdt 97105). removed first bullet point ?not recommended for new designs. the cy2305c and cy2309c are form, fit, function compatible devices with improved specifications.? from feat ures section. (cdt 99798). removed footnote 20 and all its references from document. (cdt 99798). *o 3400613 bash 10/10/2011 added footnote 10 and its reference to all pll lock time parameters throughout the document. added figure 9 for stop time illustration. *p 3859773 aju 01/07/2013 updated ordering information for cy2305 (updated part numbers). updated ordering information for cy2309 (updated part numbers). updated package drawing and dimensions : spec 51-85068 ? changed revision from *d to *e. *q 3997602 aju 05/11/2013 updated package drawing and dimensions : spec 51-85066 ? changed revision from *e to *f. added errata . *r 4124780 cinm 10/24/2013 updated in new template. completing sunset review. *s 4307827 cinm 03/13/2014 updated errata . document history page (continued) document title: cy2305/cy2309, low cost 3.3 v zero delay buffer document number: 38-07140 revision ecn orig. of change submission date description of change
document number: 38-07140 rev. *s revised march 13, 2014 page 22 of 22 all product and company names mentioned in this document may be the trademarks of their respective holders. cy2305/cy2309 ? cypress semiconductor corporation, 2001-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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